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vcxo w/3.3v, 2.5v lvpecl femtoclock? pll ics813321-04 idt ? / ics ? vcxo lvpecl femtoclock? pll 1 ics813321ag-04 rev. a november 28, 2007 g eneral d escription the ics813321-04 is a two stage device ? a vcxo followed by a femtoclock? pll. the femtoclock pll can multiply the crystal frequency of the vcxo up to a range of 122mhz to 160mhz, with a random rms phase jitter of less than 1ps (1.875mhz ? 20mhz). this phase jitter performance meets the requirements of 1gb/10gb ethernet, 1gb, 2gb, 4gb and 10gb fibre chan- nel, and sonet up to oc48. f eatures ? one 3.3v or 2.5v lvpecl output pair ? crystal operating frequency range: 14mhz - 20mhz ? vco range: 490mhz - 640mhz ? output frequency range: 122mhz - 160mhz ? vcxo pull range: 50ppm (typical apr) @ 3.3v ? supports the following applications (among others): sonet, ethernet, fibre channel ? rms phase jitter @ 156.25mhz (1.875mhz - 20mhz): 0.53ps (typical) @ 3.3v ? supply voltage modes: v cc /v cco 3.3v/3.3v 3.3v/2.5v 2.5v/2.5v ? 0c to 70c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s b lock d iagram vcxo phase detector vco 490mhz - 640mhz m = 25 (default) , 32 n = 4 0 1 q nq v c oe xtal_in xtal_out 19.44mhz pullup sel pullup vco_sel pullup p in a ssignment nc v cco q nq v ee nc v cca v cc 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vco_sel nc oe sel v c nc xtal_in xtal_out ics813321-04 16-lead tssop 4.4mm x 5.0mm x 0.92mm package body g package top view
idt ? / ics ? vcxo lvpecl femtoclock? pll 2 ics813321ag-04 rev. a november 28, 2007 ics813321-04 vcxo w/3.3v, 2.5v lvpecl femtoclock? pll t able 1. p in d escriptions t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k ? ? ? 5 1 , 1 1 , 6 , 1c nd e s u n u. t c e n n o c o n 2v o c c r e w o p. n i p y l p p u s t u p t u o 4 , 3q n , qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . s t u p t u o k c o l c l a i t n e r e f f i d 5v e e r e w o p. n i p y l p p u s e v i t a g e n 7v a c c r e w o p. n i p y l p p u s g o l a n a 8v c c r e w o p. n i p y l p p u s e r o c 0 1 , 9n i _ l a t x , t u o _ l a t xt u p n i , t u p n i e h t s i n i _ l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c . t u p t u o e h t s i t u o _ l a t x 2 1v c t u p n i. t u p n i e g a t l o v l o r t n o c o x c v 3 1l e st u p n in w o d l l u p. 3 e l b a t e e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l . n i p t c e l e s 4 1e ot u p n ip u l l u p . e v i t c a s i t u p t u o e h t , h g i h n e h w . n i p e l b a n e t u p t u o . e t a t s e c n a d e p m i h g i h a n i s i t u p t u o e h t , w o l n e h w . e c a f r e t n i l t t v l / s o m c v l 6 1l e s _ o c vt u p n ip u l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . n i p t c e l e s o c v : e t o n n w o d l l u p d n a p u l l u p . s e u l a v l a c i p y t r o f , e l b a t s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r t able 3. sel f unction t able t u p n i l o r t n o c m l e s 0) t u l a f e d ( 5 2 12 3
idt ? / ics ? vcxo lvpecl femtoclock? pll 3 ics813321ag-04 rev. a november 28, 2007 ics813321-04 vcxo w/3.3v, 2.5v lvpecl femtoclock? pll t able 4a. p ower s upply dc c haracteristics , v cc = v cco = 3.3v5%, v ee = 0v, t a = 0c to 70c a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o (lvpecl) contin uous current 50ma surge current 100ma package thermal impedance, ja 92.4c/w (0 mps) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. t able 4c. p ower s upply dc c haracteristics , v cc = v cco = 2.5v5%, v ee = 0v, t a = 0c to 70c t able 4b. p ower s upply dc c haracteristics , v cc = 3.3v5%, v cco = 2.5v5%, v ee = 0v, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 7 3 . 25 . 25 2 6 . 2v v a c c e g a t l o v y l p p u s g o l a n av c c 0 1 . 0 ?5 . 2v c c v v o c c e g a t l o v y l p p u s t u p t u o 5 7 3 . 25 . 25 2 6 . 2v i a c c t n e r r u c y l p p u s g o l a n a 0 1a m i e e t n e r r u c y l p p u s r e w o p 5 2 1a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n av c c 0 1 . 0 ?3 . 3v c c v v o c c e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i a c c t n e r r u c y l p p u s g o l a n a 0 1a m i e e t n e r r u c y l p p u s r e w o p 0 3 1a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n av c c 0 1 . 0 ?3 . 3v c c v v o c c e g a t l o v y l p p u s t u p t u o 5 7 3 . 25 . 25 2 6 . 2v i a c c t n e r r u c y l p p u s g o l a n a 0 1a m i e e t n e r r u c y l p p u s r e w o p 0 3 1a m
idt ? / ics ? vcxo lvpecl femtoclock? pll 4 ics813321ag-04 rev. a november 28, 2007 ics813321-04 vcxo w/3.3v, 2.5v lvpecl femtoclock? pll t able 4e. lvpecl dc c haracteristics , v cc = v cco = 3.3v5%, v ee = 0v, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov o c c 4 . 1 -v o c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov o c c 0 . 2 -v o c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o c c . v 2 - t able 4d. lvcmos / lvttl dc c haracteristics , t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i v c c v 3 . 3 =2v c c 3 . 0 +v v c c v 5 . 2 =7 . 1v c c 3 . 0 +v v l i e g a t l o v w o l t u p n i v c c v 3 . 3 =3 . 0 -8 . 0v v c c v 5 . 2 =3 . 0 -7 . 0v i h i t n e r r u c h g i h t u p n i , e o l e s _ o c v v c c v = n i v 5 2 6 . 2 r o v 5 6 4 . 3 =5a l e sv c c v = n i v 5 2 6 . 2 r o v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i , e o l e s _ o c v v c c v , v 5 2 6 . 2 r o v 5 6 4 . 3 = n i v 0 =0 5 1 -a l e sv c c v , v 5 2 6 . 2 r o v 5 6 4 . 3 = n i v 0 =5 -a t able 4f. lvpecl dc c haracteristics , v cc = 3.3v5% or 2.5v5%, v cco = 2.5v5%, v ee = 0v, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov o c c 4 . 1 -v o c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov o c c 0 . 2 -v o c c 5 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 4 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o c c . v 2 -
idt ? / ics ? vcxo lvpecl femtoclock? pll 5 ics813321ag-04 rev. a november 28, 2007 ics813321-04 vcxo w/3.3v, 2.5v lvpecl femtoclock? pll t able 5b. ac c haracteristics , v cc = 3.3v5%, v cco = 2.5v5%, v ee = 0v, t a = 0c to 70c t able 5a. ac c haracteristics , v cc = v cco = 3.3v5%, v ee = 0v, t a = 0c to 70c t able 5c. ac c haracteristics , v cc = v cco = 2.5v5%, v ee = 0v, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o1 = l e s _ o c v2 2 10 6 1z h m t ) ? ( t i j ; ) m o d n a r ( , r e t t i j e s a h p s m r 2 , 1 e t o n ) z h m 0 2 - z h m 5 7 8 . 1 ( z h m 2 5 . 5 5 13 5 . 0s p f o c v e g n a r k c o l o c v l l p 0 9 40 4 6z h m t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 5 20 0 6s p c d oe l c y c y t u d t u p t u o 8 42 5% . e c a f r e t n i l a t s y r c a g n i s u r e t t i j e s a h p : 1 e t o n . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 2 e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o1 = l e s _ o c v2 2 10 6 1z h m t ) ? ( t i j ; ) m o d n a r ( , r e t t i j e s a h p s m r 2 , 1 e t o n ) z h m 0 2 - z h m 5 7 8 . 1 ( z h m 2 5 . 5 5 14 6 . 0s p f o c v e g n a r k c o l o c v l l p 0 9 40 4 6z h m t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 5 20 0 6s p c d oe l c y c y t u d t u p t u o 8 42 5% . e c a f r e t n i l a t s y r c a g n i s u r e t t i j e s a h p : 1 e t o n . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 2 e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o1 = l e s _ o c v2 2 10 6 1z h m t ) ? ( t i j ; ) m o d n a r ( , r e t t i j e s a h p s m r 2 , 1 e t o n ) z h m 0 2 - z h m 5 7 8 . 1 ( z h m 2 5 . 5 5 13 5 . 0s p f o c v e g n a r k c o l o c v l l p 0 9 40 4 6z h m t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 5 20 0 6s p c d oe l c y c y t u d t u p t u o 8 42 5% . e c a f r e t n i l a t s y r c a g n i s u r e t t i j e s a h p : 1 e t o n . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 2 e t o n
idt ? / ics ? vcxo lvpecl femtoclock? pll 6 ics813321ag-04 rev. a november 28, 2007 ics813321-04 vcxo w/3.3v, 2.5v lvpecl femtoclock? pll t ypical p hase n oise at 155.52mh z 155.52mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.53ps (typical) o ffset f requency (h z ) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m 10m 100m ? ? ? dbc hz n oise p ower oc-12 filter raw phase noise data phase noise result by adding sonet oc-12 filter to raw data
idt ? / ics ? vcxo lvpecl femtoclock? pll 7 ics813321ag-04 rev. a november 28, 2007 ics813321-04 vcxo w/3.3v, 2.5v lvpecl femtoclock? pll clock outputs 20% 80% 80% 20% t r t f v sw i n g p arameter m easurement i nformation 3.3v c ore /3.3v lvpecl o utput l oad ac t est c ircuit scope qx nqx lvpecl v ee 2v -1.3v0.165v o utput d uty c ycle /p ulse w idth /p eriod 3.3v c ore /2.5v lvpecl o utput l oad ac t est c ircuit o utput r ise /f all t ime phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power rms p hase j itter -0.5v 0.125v 2.5v c ore /2.5v lvpecl o utput l oad ac t est c ircuit v cc, v cco t pw t period t pw t period odc = x 100% q nq scope qx nqx lvpecl v ee 2.8v0.04v -0.5v 0.125v v cca v cco 2.8v0.04v 2v v cca scope qx nqx lvpecl v ee 2v v cc, v cco 2v v cca 2v v cc
idt ? / ics ? vcxo lvpecl femtoclock? pll 8 ics813321ag-04 rev. a november 28, 2007 ics813321-04 vcxo w/3.3v, 2.5v lvpecl femtoclock? pll a pplication i nformation f igure 1. p ower s upply f iltering v cc v cca 3.3v or 2.5v 10 10f .01f .01f i nputs : lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput p ins p ower s upply f iltering t echniques as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter perfor- mance, power supply isolation is required. the i cs813321-04 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc , v cca , and v cco should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v cc pin and also shows that v cca requires that an additional10 resistor along with a 10f bypass capacitor be connected to the v cca pin.
idt ? / ics ? vcxo lvpecl femtoclock? pll 9 ics813321ag-04 rev. a november 28, 2007 ics813321-04 vcxo w/3.3v, 2.5v lvpecl femtoclock? pll t ermination for 3.3v lvpecl o utput v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin the clock layout topology shown below is a typical termina- tion for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, ter- minating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are f igure 2b. lvpecl o utput t ermination f igure 2a. lvpecl o utput t ermination designed to drive 50 transmission lines. matched imped- ance techniques should be used to maximize operating fre- quency and minimize signal distortion. figures 2a and 2b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
idt ? / ics ? vcxo lvpecl femtoclock? pll 10 ics813321ag-04 rev. a november 28, 2007 ics813321-04 vcxo w/3.3v, 2.5v lvpecl femtoclock? pll t ermination for 2.5v lvpecl o utput figure 3a and figure 3b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 to v cc - 2v. for v cco = 2.5v, the v cco - 2v is very close to ground level. the r3 in figure 3b can be eliminated and the termination is shown in figure 3c. f igure 3c. 2.5v lvpecl t ermination e xample r2 50 zo = 50 ohm vcco=2.5v r1 50 zo = 50 ohm + - 2.5v 2,5v lvpecl driv er f igure 3b. 2.5v lvpecl d river t ermination e xample vcco=2.5v r1 50 r2 50 zo = 50 ohm r3 18 2,5v lvpecl driv er zo = 50 ohm + - 2.5v f igure 3a. 2.5v lvpecl d river t ermination e xample r2 62.5 2.5v 2,5v lvpecl driv er r3 250 zo = 50 ohm zo = 50 ohm r4 62.5 2.5v + - r1 250 vcco=2.5v
idt ? / ics ? vcxo lvpecl femtoclock? pll 11 ics813321ag-04 rev. a november 28, 2007 ics813321-04 vcxo w/3.3v, 2.5v lvpecl femtoclock? pll vcxo c rystal s election choosing a crystal with the correct characteristics is one of the most critical steps in using a voltage controlled crystal oscillator (vcxo). the crystal parameters affect the tuning range and f igure 4. vcxo o scillator c ircuit v c - control voltage used to tune frequency c v - varactor capacitance, varies due to the change in control voltage c l1, c l2 - load tuning capacitance used for fine tuning or centering nominal frequency c s1, c s2 - stray capacitance caused by pads, vias, and other board parasitics accuracy of a vcxo. below are the key variables and an example of using the crystal parameters to calculate the tuning range of the vcxo. oscillator v c c v c s1 c l1 c s2 c l2 c v xtal vcxo (internal) optional ? ? ? ? ? control voltage t able 6. e xample c rystal p arameters l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f n y c n e u q e r f l a n i m o n 4 10 2z h m f t e c n a r e l o t y c n e u q e r f 0 2 m p p f s y t i l i b a t s y c n e u q e r f 0 2 m p p e g n a r e r u t a r e p m e t g n i t a r e p o 00 7c c l e c n a t i c a p a c d a o l 2 1f p c o e c n a t i c a p a c t n u h s 4f p c , 1 c 2 o i t a r y t i l i b a l l u p 0 2 20 4 2 r s ee c n a t s i s e r s e i r e s t n e l a v i u q e 0 2 l e v e l e v i r d 1w m c 5 2 @ g n i g a r a e y r e p 3 m p p n o i t a r e p o f o e d o m l a t n e m a d n u f
idt ? / ics ? vcxo lvpecl femtoclock? pll 12 ics813321ag-04 rev. a november 28, 2007 ics813321-04 vcxo w/3.3v, 2.5v lvpecl femtoclock? pll l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c w o l _ v e c n a t i c a p a c r o t c a r a v w o lv c v 0 =6f p c h g i h _ v e c n a t i c a p a c r o t c a r a v h g i hv c v 3 . 3 =1 1f p t able 7. v aractor p arameters f ormulas ( ) ( ) ()( ) low v s l low v s l low v s l low v s l low c c c c c c c c c c c c c _ 2 2 _ 1 1 _ 2 2 _ 1 1 + + + + + + + ? + + = ( ) ( ) ()( ) high v s l high v s l high v s l high v s l high c c c c c c c c c c c c c _ 2 2 _ 1 1 _ 2 2 _ 1 1 + + + + + + + ? + + = 6 0 1 0 0 1 0 10 1 2 1 1 2 1 ) ( ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? + ? ? = c c c c c c c c tpr range pull t otal high low ?c low is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance. c low determines the high frequency component on the tpr. ?c high is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance. c high determines the low frequency component on the tpr. absolute pull range (apr) = total pull range ? (frequency tolerance + frequency stability + aging) e xample c alculations using the tables and figures above, we can now calculate the tpr and apr of the vcxo using the example crystal parameters. for the numerical example below there were some assumptions made. first, the stray capacitance (c s1 , c s2 ), which is all the excess capacitance due to board parasitic, is 4pf. second, the expected lifetime of the project is 5 years; hence the inaccuracy due to aging is 15ppm. third, though many boards will not require load tuning capacitors (c l1 , c l2 ), it is recommended for long-term consistent performance of the system that two tuning capacitor pads be placed into every design. typical values for the load tuning capacitors will range from 0 to 4pf. tpr = 106ppm apr = 106ppm ? (20ppm + 20ppm + 15ppm) = 51ppm the example above will ensure a total pull range of 106 ppm with an apr of 51ppm. many times, board designers may select their own crystal based on their application. if the application requires a tighter apr, a crystal with better pullability (c0/c1 ratio) can be used. also, with the equations above, one can vary the frequency tolerance, temperature stability, and aging or shunt capacitance to achieve the required pullability. 1 ? ? ? ? ? ? ? ? ? ? 1 2 220 ( 1 + 9.5 p ? 4 p ? ) 2 220 ( 1 + 15.7 p ? 4 p ? ) 1 ? tpr = 10 6 = 212ppm c low = (0 + 4 p ? + 15 p ? ) (0 + 4 p ? + 15 p ? ) (0 + 4 p ? + 15 p ? ) (0 + 4 p ? + 15 p ? ) = 9.5p ? c high = (0 + 4 p ? + 27.4 p ? ) (0 + 4 p ? + 27.4 p ? ) (0 + 4 p ? + 27.4 p ? ) (0 + 4 p ? + 27.4 p ? ) = 15.7p ?
idt ? / ics ? vcxo lvpecl femtoclock? pll 13 ics813321ag-04 rev. a november 28, 2007 ics813321-04 vcxo w/3.3v, 2.5v lvpecl femtoclock? pll p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics813321-04. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics813321-04 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 130ma = 450mw total power _max (3.465v, with output switching) = 450mw + 30mw = 480mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 92.4c/w per table 8 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.480w * 92.4c/w = 114.4c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 8. t hermal r esistance ja for 16- pin tssop, f orced c onvection ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 92.4c/w 88.0c/w 75.91c/w
idt ? / ics ? vcxo lvpecl femtoclock? pll 14 ics813321ag-04 rev. a november 28, 2007 ics813321-04 vcxo w/3.3v, 2.5v lvpecl femtoclock? pll 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 5. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cco ? 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max ? v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max ? v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v oh_max ) = [(2v ? (v cco _max ? v oh_max )) /r l ] * (v cco_max ? v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v ol_max ) = [(2v ? (v cco _max ? v ol_max )) /r l ] * (v cco_max ? v ol_max ) = [(2v ? 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 5. lvpecl d river c ircuit and t ermination v out v cco v cco - 2v q1 rl 50
idt ? / ics ? vcxo lvpecl femtoclock? pll 15 ics813321ag-04 rev. a november 28, 2007 ics813321-04 vcxo w/3.3v, 2.5v lvpecl femtoclock? pll r eliability i nformation t ransistor c ount the transistor count for ics813321-04 is: 3948 t able 9. ja vs . a ir f low t able for 16 l ead tssop ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 92.4c/w 88.0c/w 75.91c/w
idt ? / ics ? vcxo lvpecl femtoclock? pll 16 ics813321ag-04 rev. a november 28, 2007 ics813321-04 vcxo w/3.3v, 2.5v lvpecl femtoclock? pll p ackage o utline - g s uffix for 16 l ead tssop t able 10. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n6 1 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 9 . 40 1 . 5 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0
idt ? / ics ? vcxo lvpecl femtoclock? pll 17 ics813321ag-04 rev. a november 28, 2007 ics813321-04 vcxo w/3.3v, 2.5v lvpecl femtoclock? pll t able 11. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 4 0 - g a 1 2 3 3 1 8 s c i4 0 a 1 2 3 3 1p o s s t d a e l 6 1e b u tc 0 7 o t c 0 t 4 0 - g a 1 2 3 3 1 8 s c i4 0 a 1 2 3 3 1p o s s t d a e l 6 1l e e r & e p a t 0 0 5 2c 0 7 o t c 0 f l 4 0 - g a 1 2 3 3 1 8 s c il 4 0 a 1 2 3 3p o s s t " e e r f - d a e l " d a e l 6 1e b u tc 0 7 o t c 0 t f l 4 0 - g a 1 2 3 3 1 8 s c il 4 0 a 1 2 3 3p o s s t " e e r f - d a e l " d a e l 6 1l e e r & e p a t 0 0 5 2c 0 7 o t c 0 . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature ranges, high reliability or other extraordina ry environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or w arrant any idt product for use in life support devices or critical medical instruments.
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